Lockheed Martin
Orlando, FL, USA
Description: You will be the Senior ASIC & FPGA Design Engineer for the Multi Domain Missile Warning Payload team. Our team creates large format, high frame rate imaging sensor systems that provide survivability enhancing situational awareness for air, space and surface platforms. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will work side by side with a PLD subject matter expert to architect, design and implement programmable logic solutions for the imaging sensor system. You will integrate hardware, develop test plans and verify performance on demanding space based platforms, contributing to a scalable, high performance missile warning payload. Your responsibilities will include: • Define architecture and design specifications for programmable logic components, develop and document RTL (VHDL/Verilog/SystemVerilog) gate level designs that meet performance, power, and reliability requirements. • Create synthesis, place and route, and timing...