8 engineering jobs found

Position: Test Automation Engineer Job Description: Must Have: Web and Mobile Application Automation , API Automation Unit, Function, Integration Test Script Development, Code Review, Execution, Analysis, Debugging Languages/Tools/Technologies: Python, Selenium, Appium, Playwright Good to have: Embedded Device Testing Dockerization, CI/CD pipeline Location: IN-GJ-Ahmedabad, India-Ognaj (eInfochips) Time Type: Full time Job Category: Engineering Services

Position: DFT Engineer- eInfochips Job Description: Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services

Position: Technical Lead (Silicon Validation) Job Description: Experience:  10-15 Years  What You'll Be Doing Principal Accountabilities: Lead pre & post-silicon functional validation activities for complex SoCs, MCUs, and ASICs. Drive board bring-up covering power, reset, clock, straps, fuses, hardware initialization, and JTAG debug. Develop and execute validation plans, test cases, and debug strategies for functional and system-level validation. Lead hardware debug and failure analysis by performing root cause investigations of boot failures, system hangs, data corruption, memory access issues, and intermittent hardware failures. Validate and debug interfaces such as PCIe, Ethernet, CAN/CAN FD, LIN, FlexRay, UART, I2C, and SPI. Perform Lab Validation & debugging using oscilloscopes, logic analyzers, protocol analyzers, bus sniffers, and JTAG. Validate SRAM/Flash and debug memory initialization, access, and data integrity issues. Read schematics...

Position: Analog Design Engineer- eInfochips Job Description: Analog designer with experience of 5 to 8 Years of experience in below, CT sigma delta ADC,  RFIC design: LNA and mixer, PLLs Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, RFIC). EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro).  Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…) nodes. Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling...

Position: Senior ASIC RTL Design Engineer Job Description: Location: IN-UP-Noida, India-World Trade Tower (eInfochips) Time Type: Full time Job Category: Engineering Services

Position: Senior Engineer - Mixed Signal Job Description: Location: IN-MH-Pune, India-Blue Ridge-Hinjewadi (eInfochips) Time Type: Full time Job Category: Engineering Services

Position: Senior Engineer RTL Design Job Description: Principal Accountabilities * RTL development for ASIC / FPGA * Responsible for completion of front end design flow (spec to RTL / Netlist)  * Design, micro architect & do RTL coding, Lint, CDC * Support existing sustenance designs  * Collaborate with Hardware board design engineers for system level designs, Board level block diagram design and validation of hardware, utilizing the Company specified hardware design tools Job Complexity ● Requires in-depth knowledge and experience ● Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience ● Represents the level at which career may stabilize for many years or even until retirement ● Contributes to process improvements ● Typically resolves problems using existing solutions ● Provides informal guidance to junior staff ● Works with minimal guidance...

Position: Senior Physical Design Engineer Job Description: Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services