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2 advanced asic fpga engineer jobs found in Orlando

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Lockheed Martin
Apr 21, 2026
ASIC & FPGA Design Engineer
Lockheed Martin Orlando, FL
Description: You will be the FPGA/ASIC Design Engineer for the Advanced Programs area. Our team accelerates high performance hardware development by partnering with cross functional engineers to move concepts through design, procurement, testing, and the Design Assurance process. What You Will Be Doing As the FPGA/ASIC Design Engineer you will own the end to end creation of complex FPGA and ASIC solutions—defining specifications, architecting designs, verifying functionality, and implementing hardware that meets strict power, thermal, and utilization goals. You will work side by side with software, hardware, and systems engineers to shape optimal architectures and drive rapid, reliable delivery. Your responsibilities will include: • Develop detailed FPGA/ASIC specifications, high level architecture, and RTL implementation using VHDL/Verilog. • Perform functional and timing verification, creating testbenches, simulation plans, and hardware in the loop validation. • Conduct...
Lockheed Martin
Mar 17, 2026
FPGA Design Engineer Sr
Lockheed Martin Orlando, FL
Description: You will be the FPGA Design & Verification Engineer for the Lockheed Martin Advanced Technologies team. Our team creates cutting edge FPGA based solutions that power next generation defense and aerospace systems, delivering high performance computing, signal processing and real time control. What You Will Be Doing As the FPGA Design & Verification Engineer you will capture and derive system requirements, design, simulate and integrate FPGA architectures, and develop verification environments. You will troubleshoot existing designs, implement updates, and build new FPGA solutions from concept through production, working closely with the Programmable Logic Design Lead and cross functional engineers. Your responsibilities will include: • Translating system requirements into detailed FPGA designs, writing HDL code (SystemVerilog preferred, VHDL acceptable) and generating synthesis, placement, routing and timing constraints. • Developing self checking...
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