6 jobs found in San Jose

Position: Design Verification Engineer IV Job Description: Principal Accountabilities * Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development  * Develop complex self checking test benches with constraint random stimulus generation. * Architect SoC test FW and create test plan documentation to cover ASIC features. * Develop and debug SoC ASIC platform test FW and specific tests in C/C++. * Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification objective. * Develop/modify scripts to automate the verification process. * Develop verification environment including environment assumptions, assertions, and cover properties in context of the...

Position: Design Verification Engineer Job Description: Principal Accountabilities * Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect * Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience ● Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience ● Represents the level at which career may stabilize for many years or even until retirement ● Contributes to process improvements ● Typically resolves problems using existing solutions ● Provides informal...

Position: Design Verification Engineer (eInfochips) Job Description: What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap → Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available What we are looking for: A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Verification closure with team Make/Perl/Python  Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively Education: Bachelor's degree required Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow...

Basic Qualifications Bachelor’s degree or equivalent is required plus a minimum of 8 years relevant experience; or Master's degree plus a minimum of 6 years relevant experience to meet managerial expectations. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is required at time of hire. The selected candidate must be able to obtain a Polygraph within a reasonable amount of time from date of hire.  Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position The responsibility is career-defining. So is the opportunity. At General Dynamics Mission Systems, we invent the technologies, products and services, that help our nation’s heroes keep our nation safe. The work is so advanced, our...

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote)  What will you do: Strong expertise on Arteris/ NOC Design Toolset  At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C based processor Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What we are looking for: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. Experience in complete verification cycle which includes development of test plan,  BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great...

Basic Qualifications Requires a Bachelor’s degree in Systems Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience. Agile experience preferred.   CLEARANCE REQUIREMENTS:  Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position GDMS Sr. Advanced Systems Engineers analyze, design, develop and test GDMS systems to ensure the integration of software, hardware, reliability, maintainability, safety and other requirements in the total engineering effort.   Responsibilities include...