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2 technical intern jobs found

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Information Technology technical intern Arizona
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General Dynamics Mission Systems, Inc  (2)
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General Dynamics Mission Systems, Inc
Jun 08, 2026
Chief Architect- Space Communication Systems
General Dynamics Mission Systems, Inc Scottsdale, AZ
Basic Qualifications Bachelor's degree in Engineering, plus a minimum of 15 years of relevant experience; or Master's degree in Engineering, plus a minimum of 13 years of relevant experience.   Clearance Requirements: Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.   Responsibilities for this Position Ready to be a leader with the company that is committed to pushing the limits of truly advanced technologies? At General Dynamics Mission Systems, we create the products and services that help our service members, intelligence analysts and first...
General Dynamics Mission Systems, Inc
May 18, 2026
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc Scottsdale, AZ
Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.   CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position What You'll Do Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families. Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming,...
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