6 device engineer jobs found in San Jose

Position: Design Verification Engineer (eInfochips) Job Description: What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap → Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available What we are looking for: A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Verification closure with team Make/Perl/Python  Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively Education: Bachelor's degree required Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow...

Basic Qualifications Education Requirements: Bachelor’s degree in Engineering, a related specialized area or field is required (or equivalent experience) plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience. Clearance Requirements: Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Developing mission-critical systems that help keep people safe is what we do. At General Dynamics Mission Systems, you’ll be part of the team that helps heroes make a true impact. The work we do is important. The challenges we face are career-defining. The opportunity we can...

Position: Design For Test Engineer III (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to...

Basic Qualifications Bachelor’s degree or equivalent is required plus a minimum of 8 years relevant experience; or Master's degree plus a minimum of 6 years relevant experience to meet managerial expectations. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is required at time of hire. The selected candidate must be able to obtain a Polygraph within a reasonable amount of time from date of hire.  Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position The responsibility is career-defining. So is the opportunity. At General Dynamics Mission Systems, we invent the technologies, products and services, that help our nation’s heroes keep our nation safe. The work is so advanced, our...

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote)  What will you do: Strong expertise on Arteris/ NOC Design Toolset  At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C based processor Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What we are looking for: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. Experience in complete verification cycle which includes development of test plan,  BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great...