6 engineer senior engineer jobs found in San Jose

Basic Qualifications Requires a Bachelor’s degree in Systems Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience. Agile experience preferred.   CLEARANCE REQUIREMENTS:  Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position GDMS Sr. Advanced Systems Engineers analyze, design, develop and test GDMS systems to ensure the integration of software, hardware, reliability, maintainability, safety and other requirements in the total engineering effort.   Responsibilities include...

Position: Design Verification Engineer Job Description: Principal Accountabilities * Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect * Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience ● Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience ● Represents the level at which career may stabilize for many years or even until retirement ● Contributes to process improvements ● Typically resolves problems using existing solutions ● Provides informal...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Design Verification Engineer (eInfochips) Job Description: What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap → Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available What we are looking for: A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Verification closure with team Make/Perl/Python  Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively Education: Bachelor's degree required Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow...

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to...

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote)  What will you do: Strong expertise on Arteris/ NOC Design Toolset  At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C based processor Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What we are looking for: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. Experience in complete verification cycle which includes development of test plan,  BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great...