18 jobs found in Santa Clara, CA

Position: Design Verification Engineer III Job Description: Annual Hiring Range/Hourly Rate: $95,900.00 - $126,280.00 Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.   Location: US-CA-California (Remote Employees)   Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company’s request and sole discretion. Time Type: Full time Job Category: Engineering Services EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.  (Arrow EEO/AAP policy) All Arrow job postings...

Position: Infrastructure Engineer (einfochips) Job Description: What You'll Be Doing: Partner with silicon design, verification, emulation, and software teams to understand their development workflows, pain points, and iteration cycles. Build tooling and automation that eliminates manual toil and reduces time-to-results. Gather continuous feedback from internal customers and rapidly iterate on solutions. Benchmark infrastructure based on silicon development workflows to provide internal customers with the optimal resources for silicon development. Own Platform Delivery and Operations Design, implement, and operate cloud infrastructure and high-performance computing clusters using schedulers like Slurm. Build and maintain CI/CD pipelines for infrastructure-as-code and service deployments with comprehensive testing and safe rollback mechanisms. Take ownership of platform reliability, performance, and cost efficiency from initial design through production operation....

Position: Post-Silicon Systems Software Validation Engineer Job Description: - Strong programming skills (Python, Lua, C/C++, Rust, Go, etc) - A solid understanding of computer architecture and chip/system validation methodologies - Firmware testing and/or development (BIOS, BMC, drivers) - Domain expertise in any of these areas: PCIe, HBM, GPUs, neural networks, ML HW architecture - Knowledge of the full validation lifecycle from RTL simulation (SystemVerilog/UVM, VCS, Questa, Xcelium) and emulation (Palladium, Zebu, Veloce) through silicon failure analysis and debug - 5+ years of programming with at least one software programming language experience - Bachelor's degree or above in computer science, computer engineering, or related field, or Bachelor's degree - Experience with Linux environments and Git. - Experience with server hardware and debug tools - Experience with Machine Learning Hardware/Software Architecture - Experience with CI/CD - Experience with EDA...

Position: Pre-Sales Solutions Architect - IBM Job Description: Arrow is   seeking   a highly skilled and motivated IBM   Hybrid Cloud and Power   to support our client base in the Americas region. This role will provide lead efforts in partner enablement & recruitment and technical   expertise   in support of pre-sales activities. This person will   assist   in the IBM   Hybrid Cloud and Power   sales cycle including partner and customer discovery, analysis, design, demonstration, and refinement of technology solutions. There is a technical emphasis on offerings including OpenShift, Hybrid Cloud, on-prem and deployments.  This role involves supporting sales teams, presenting technical demonstrations, and providing product   expertise . The successful candidate will develop general knowledge across all IBM   Hybrid Cloud and Power   offerings with a focus on Modernization and IT areas generally and may also   assist   in responding to...

Position: Physical Design Engineer II (IC) Job Description: Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. Minimum Qualifications: Bachelor's degree...

Position: Design For Test Engineer III (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Timing Constraints Engineer (eInfochips) Job Description: Location: US-CA-San Jose, California (eInfochips) Time Type: Full time Job Category: Engineering Services EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.  (Arrow EEO/AAP policy) All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.

Position: Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development. Develop complex self checking test benches with constraint random stimulus generation. Architect SoC test FW and create test plan documentation to cover ASIC features. Develop and debug SoC ASIC platform test FW and specific tests in C/C++. Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents. Implement and maintain integrated end-to-end formal verification flow for the formal verification objective....

Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor's degree...

Position: Design Verification Engineer(eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect  Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience  Represents the...

Position: Market Development Engineer Job Description: This Market Development Engineer will be primarily responsible for supporting customer’s technical needs around low power IoT Wireless electronic components like WiFi, Bluetooth, ZigBee and Thread SoCs.  In addition, the ideal candidate should also have strong background in ARM-based multi-core application processor solutions (32-bit and 64-bit) from suppliers like Qualcomm.  What You'll Be Doing Responsible for utilizing an advanced understanding of the customer needs and technical leadership expertise to champion return on engineering investment. • Drive demand creation by maximizing Arrow content on designs. Understand customer needs and leverage Arrow’s engineering and design services resources to facilitate solutions for customers. Apply technical knowledge to influence designs utilizing solution selling, resources, and strategies.  Partner with the sales team across pre-and post-sales activities, providing...

Position: Field Applications Engineer (Altera FPGA) Job Description: Arrow Electronics is a global provider of products, services, and solutions to industrial and commercial users of electronic components and enterprise computing solutions. Arrow Electronics guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2025 sales of $30.9 billion, Arrow develops technology solutions that improve business and daily life. The company maintains 228 locations worldwide with over 85 countries served. A Fortune 148 company with 21,500 employees worldwide, Arrow brings technology solutions to a breadth of markets, including telecommunications, information systems, transportation, medical, industrial, and consumer electronics. Arrow provides specialized services and expertise across the entire product lifecycle. Arrow does this by connecting customers to the right technology at the right place, time, and price. Arrow provides extraordinary...

Position: FPGA Engineer Engineer (eInfochips) Job Description: Job Description Location: San Jose CA and Austin TX (Day-1 Onsite) Experience: 9+ Years What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals....

Position: Field Sales Representative II Job Description: RichardsonRFPD , (Radio Frequency & Power Division). Inc. is a global leader in the RF, (Radio Frequency), wireless communications market, IoT and power technologies. Richardson RFPD, an Arrow Electronics company, is a global leader in the RF and wireless communications, power conversion and renewable energy markets. It brings relationships with many of the industry’s top radio frequency and power component suppliers. Whether it’s designing components or engineering complete solutions, Richardson RFPD’s worldwide design centers and technical sales team provide comprehensive support for customers’ go-to-market strategy, from prototype to production. What You'll Be Doing: Define critical markets and new customers in the San Jose/Bay Area, plan strategy and develop all key relationships to ensure strong foundation for solution selling. Maintain and promote relationships with customer contacts who may be...

Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to...

Position: ASIC Design Engineer (eInfochips) Job Description: Role:   Asic Design Engineer Location: Mountain View CA (Remote) Note:   Seeking candidate with Fusion Compiler and Scripting experince. What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing...