27 cloud engineer jobs found

Position: Sr. Linux Red Hat Infrastructure Engineer Job Description: Arrow Electronics is a global provider of products, services, and solutions to industrial and commercial users of electronic components and enterprise computing solutions. Arrow Electronics guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2025 sales of $30.9 billion, Arrow develops technology solutions that improve business and daily life. The company maintains 228 locations worldwide with over 85 countries served. A Fortune 148 company with 21,500 employees worldwide, Arrow brings technology solutions to a breadth of markets, including telecommunications, information systems, transportation, medical, industrial, and consumer electronics. Arrow provides specialized services and expertise across the entire product lifecycle. Arrow does this by connecting customers to the right technology at the right place, time, and price. Arrow provides extraordinary...

Position: Software Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Experience and knowledge in complex embedded software architecture and design. Design knowledge of CAN, I2C, SPI, RS232 protocols Strong knowledge of programming in C, C++ for various embedded controllers and processors SW V&V (Verification and Validation is mandatory ), Perform software testing including unit, functional and system level requirement including manual and automated experience in Integration - design and development of embedded software/firmware Participate software design Excellent debugging skills Well versed with configuration management tools What we are looking for: A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 7 years of experience. Participate software design Excellent debugging skills Well versed with configuration management tools What’s In It for You: At Arrow, we recognize that financial...

Position: Hardware Engineer (eInfochips Inc) Job Description: What You'll Be Doing: The Electronics Engineer will be responsible for the research, analysis, design, development, testing, debugging and modification of electronics equipment such as VFMDs (Variable Frequency Motor Drives) for vacuum generators and air compressors (ACIM/BLDC), AC/DC Power Converters (3-Φ), 28V DC Valve Controllers, and W&W System Controllers for commercial aerospace industry. The Electronics Engineer will take ownership and/or support technical engineering teams and projects related to W&W System Components. Using sound engineering principles, this engineer will interface with cross functional groups (internal and external) to ensure robust, airworthy designs are attained which meet budget, schedule and internal requirements and goals. What we are looking for: A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 7 years of experience....

Position: Sr Engineer (Embedded) - Einfochips Inc Job Description: What You'll Be Doing: Principal Accountabilities Design, analyze, and develop product solutions using established programming languages, tools, and security baselines. Enhance and maintain development and testing frameworks to ensure reusability, scalability, stability, and optimal performance. Prepare and execute comprehensive test plans; develop automated and manual test scripts to validate new features and improve existing products. Conduct reviews in alignment with standards and perform analysis; troubleshoot and resolve product issues of moderate complexity. Document technical deliverables throughout the project lifecycle, including specifications, design documents, code comments, test cases, test reports, and release notes. Collaborate with other technical leads to develop unit test; ensure thorough documentation. Provide guidance and support to junior team members, fostering technical growth...

Position: Infrastructure Engineer (einfochips) Job Description: What You'll Be Doing: Partner with silicon design, verification, emulation, and software teams to understand their development workflows, pain points, and iteration cycles. Build tooling and automation that eliminates manual toil and reduces time-to-results. Gather continuous feedback from internal customers and rapidly iterate on solutions. Benchmark infrastructure based on silicon development workflows to provide internal customers with the optimal resources for silicon development. Own Platform Delivery and Operations Design, implement, and operate cloud infrastructure and high-performance computing clusters using schedulers like Slurm. Build and maintain CI/CD pipelines for infrastructure-as-code and service deployments with comprehensive testing and safe rollback mechanisms. Take ownership of platform reliability, performance, and cost efficiency from initial design through production operation....

Position: Embedded Engineer- III (IC)- eInfochips Job Description: Location: Bedford, MA (Day-1 Onsite) Experience: 8+ Years What You'll Be Doing: Working on next generation Blood analyzer devices that run embedded microprocessors and microcontrollers with different sensors and motors. Looking for an individual contributor who can work on microcontrollers running Linux operating system and BareMetal Firmware. Candidate should be able to prepare architecture and design for firmware/application for embedded products. Candidates should work independently for firmware/application development in client projects and lead technical discussions with customers. Should use in-depth knowledge and experience on Embedded firmware development to overcome the challenges faced by teams for smooth execution. Should be able to do testing and validate the deliverables in Lab What We Are Looking For: Prepare architecture and design for firmware/application for...

Position: Post Silicon Engineer (eInfochips) Job Description:   Location: Cupertino, CA and Austin TX Experience: 8+ Years What You'll Be Doing: As a Senior Validation Engineer on our Machine Learning Acceleration team to work —from early design validation through emulation, silicon bring-up, post-silicon validation, and ongoing support of production systems deployed in AWS data centers. You'll collaborate deeply with architecture, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the highest standards of quality and performance. This role requires bridging multiple domains and broad scope of impact—from low-level hardware interfaces to high-level ML workloads—to deliver exceptional results. A day in the life Developing comprehensive validation strategies and leads new methodologies to improve validation coverage and time to root cause. Role models detailed test plans covering functional,...

Position: Senior Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Testbenches: Build scalable verification environments using UVM and SystemVerilog. Planning: Create detailed verification plans from architectural specifications. Execution: Write, run, and debug constrained-random tests and directed tests. Coverage: Define, measure, and close functional and code coverage metrics. Gate-Level: Run gate-level simulations to verify power-up and timing states. Automation: Develop scripts to automate regression runs and triage failures. What We Are Looking For: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Languages: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl). Methodology: Hands-on experience with UVM (Universal Verification Methodology) Tools: Experience with industry-standard simulators Cadence Xcelium preferred, but experience with Synopsys...

Position: Design Verification Engineer IV Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development. Develop complex self checking test benches with constraint random stimulus generation. Architect SoC test FW and create test plan documentation to cover ASIC features. Develop and debug SoC ASIC platform test FW and specific tests in C/C++. Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents. Implement and maintain integrated end-to-end formal verification flow for the formal verification objective....

Position: FPGA Engineer Engineer (eInfochips) Job Description: Job Description Location: San Jose CA and Austin TX (Day-1 Onsite) Experience: 9+ Years What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals....

Position: Hardware Engineer(eInfochips Inc) Job Description: What You'll Be Doing: Gather requirements and finalize the architecture for the next-gen HMI module based on various SoCs including Qualcomm and NXP, Reneses, ESP Electronics Design & Development, select components and design schematics, collaborate with customer on component placement and PCB size. Do layout design and high-speed interface guidelines, perform signal integrity, power integrity, and thermal analysis and review Gerber files. Testing Design sensor boards (Motion, Light, Accelerometer, Temperature, Gyroscope, Magnetometer, calibrate sensors) and integrate with HMI Module. Protocol experience in SPI, I2C, Serial, UART, USB, DSI, CSI Coordinate with fabrication, assembly, and integration teams, conduct bring-up, functional, EDVT, thermal, and performance testing. What We Are Looking For: Experience / Education Typically requires a 4 year degree in electrical/electronics and a minimum...

Position: Hardware Engineer Job Description: What You'll Be Doing: Gather requirements and finalize the architecture for the next-gen HMI module based on various SoCs including Qualcomm and NXP, Reneses, ESP Electronics Design & Development, select components and design schematics, collaborate with customer on component placement and PCB size. Do layout design and high-speed interface guidelines, perform signal integrity, power integrity, and thermal analysis and review Gerber files. Testing Design sensor boards (Motion, Light, Accelerometer, Temperature, Gyroscope, Magnetometer, calibrate sensors) and integrate with HMI Module. Protocol experience in SPI, I2C, Serial, UART, USB, DSI, CSI Coordinate with fabrication, assembly, and integration teams, conduct bring-up, functional, EDVT, thermal, and performance testing. What We Are Looking For: Experience / Education Typically requires a 4 year degree in   electrical/electronics   and a minimum of 8...

Position: Design Verification Engineer Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect  Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience  Represents the level at which...

Position: Design Verification Engineer (Einfochips) Job Description: Experience: 6+ Years Location: Austin TX and San Jose CA   Job Description: What candidate will Be Doing: At-least   6+ years of experience   in   System Verilog HVL and C++/C At-least 6+ year of experience in   UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in   SVTB/UVM, C++ testbench Understand DSP is a plus Subversion for Repository and Bugzilla is also a Plus Proficient in debug   and assertions coding Verification closure with team What We Are Looking For: At-least 6 + years of experience   in   System Verilog HVL and C++/C At-least 6+ year of experience in   UVM. Make/Perl/Python / any script Any protocol experiace is fine...

Position: ASIC Design Engineer (eInfochips) Job Description: Role:   Asic Design Engineer Location: Mountain View CA (Remote) Note:   Seeking candidate with Fusion Compiler and Scripting experince. What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing...

Position: Device Engineer Job Description: What You'll Be Doing: Perform Development and Verification for Flight Management system for avionics applications. Developing High Level and Low Level requirements from system requirements Analyze System level architectural requirements and use it for Design and Development of Software Requirements. Providing technical analysis by reviewing the artifacts What We Are Looking For: Bachelor’s Degree in Electrical or Computer Engineering. Development of Test cases and Test procedures execution. Generation of Test results and reports for the execution. Developing support utilities to reduce the cycle time and enhance the process. Perform Dry Run and RFS related activities. Co-ordination and team player What’s In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including...

Position: Device Engineer (eInfochips) Job Description: Role: Embedded Engineer (BSP) Location: Peachtree City GA (Day-1 Onsite) What candidate will Be Doing: Design, develop, and optimize software solutions for Android Automotive OS and Linux BSP platforms.  Coordinate closely with cross-functional teams spanning Software, Validation, and Electrical disciplines to ensure seamless integration and delivery.  Communicate with external technology partners on a weekly basis, aligning on deliverables, technical roadmaps, and issue resolution.  Drive technical decisions, conduct code reviews, and uphold best engineering practices across the team.  Collaborate with hardware and systems teams to support software integration across vehicle platforms.  What we are looking for: Typically requires a 4 year degree and a minimum of 5 years of related experience; or an advanced degree without experience; or equivalent work experience Work Arrangement...

Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT...

Position: Senior DFT Engineer (Einfochips) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...