3 electronics engineer iii jobs found

Position: Logistics Engineer III Job Description: The logistics industrial engineer leads continuous improvement initiatives across Arrow’s distribution centers in Mexico. This role partners with Operations, IT, Maintenance, Quality, Safety, external contractors, and other functional teams to improve safety, quality, productivity, cost, and service levels. The position is responsible for optimizing inbound, picking, and outbound warehouse processes; developing workflows and process maps; improving workstation and facility layouts; supporting material-handling and automation technologies; and delivering capital and operational improvement projects. The logistics industrial engineer applies engineering methods, data analysis, and project management to improve capacity, reduce waste and complexity, and establish scalable best practices across the distribution network. What You'll Be Doing:   ​ Process Optimization & Layout Design: Engineered end-to-end warehouse...

Position: Logistics Engineer III Job Description:   The logistics industrial engineer leads continuous improvement initiatives across Arrow’s distribution centers in the Americas. This role partners with Operations, IT, Maintenance, Quality, Safety, external contractors, and other functional teams to improve safety, quality, productivity, cost, and service levels. The position is responsible for optimizing inbound, picking, and outbound warehouse processes; developing workflows and process maps; improving workstation and facility layouts; supporting material-handling and automation technologies; and delivering capital and operational improvement projects. The logistics industrial engineer applies engineering methods, data analysis, and project management to improve capacity, reduce waste and complexity, and establish scalable best practices across the distribution network. What You'll Be Doing:   ​ Process Optimization & Layout Design: Engineered...

Position: Design For Test Engineer III (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...