10 device engineer jobs found

Position: Device Engineer (Einfochips Inc) Job Description: What candidate will Be Doing: Job Complexity : J ob complexity may vary among jobs within this job level and will align with one of the job complexities listed below (1) Incumbent has knowledge and experience in own discipline and may still be acquiring higher level knowledge and skills. Incumbent builds knowledge of the organization, processes and customers, solves a range of straightforward problems, and analyzes possible solutions using standard procedures. A moderate level of guidance and direction is provided. (2) Incumbent has extensive knowledge and experience in own discipline, possesses strong knowledge of the organization, processes and customers, solves a range of complex problems, and analyzes possible solutions using standard procedures. Limited guidance and direction is provided. What We are looking for Bachelor's degree in Computer Science, Computer Engineering, Information...

Position: Embedded Engineer (eInfochip Inc) Job Description: NOTE: This role will perform work covered by International Traffic in Arms Regulations. Viable candidates for this position must be eligible for an export license or be a U.S. Person (which includes but is not limited to U.S. citizens or nationals, lawful permanent residents, refugees, and asylees). What You'll Be Doing: Compliance Requirement: Must be ITAR Compliant (U.S. Person – Citizen/Green card) Hands-on experience with Qualcomm QCS platforms (QCS6490, QCS8550, QCS5430, QCS610, QCS8250 or similar) Strong Embedded Linux development experience Expertise in C/C++ programming Experience with board bring-up and hardware-software integration BSP, Linux Kernel, Device Tree, and Device Driver development Experience debugging bootloader, kernel, and platform bring-up issues Familiarity with ARM-based architectures What we are looking for: Experience interfacing peripherals such as UART, SPI, I2C,...

Position: Embedded Firmware Engineer (eInfochips Inc) Job Description: NOTE: This role will perform work covered by International Traffic in Arms Regulations. Viable candidates for this position must be eligible for an export license or be a U.S. Person (which includes but is not limited to U.S. citizens or nationals, lawful permanent residents, refugees, and asylees). What You'll Be Doing: This is similar role is similar to embedded network engineer experienced  DO-178C  SOI-2 Dev Engineer to support certification of  Time-Sensitive Networking (TSN)  software for safety-critical avionics platforms. The engineer will participate in Software Development Reviews (SOI-2) by evaluating software requirements, architecture, detailed design, traceability, and compliance with DO-178C objectives. The role involves reviewing  TSN software components such as IEEE 802.1AS (gPTP), IEEE 802.1Qbv Time-Aware Shaper, IEEE 802.1Qav Credit-Based Shaper, IEEE 802.1CB FRER, ENETC...

Position: SOC/IP Integration Engineer (eInfochips) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration. Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What We Are Looking For: Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions Works independently; receives minimal guidance Acts as a resource for colleagues with less experience Represents the level at which career may stabilize for many years or even until retirement Contributes to process improvements Typically resolves problems using...

Position: Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure   What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development. Develop complex self checking test benches with constraint random stimulus generation. Architect SoC test FW and create test plan documentation to cover ASIC features. Develop and debug SoC ASIC platform test FW and specific tests in C/C++. Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents. Implement and maintain integrated end-to-end formal verification flow for the formal verification objective....

Position: SOC/IP Integration Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration. Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What We Are Looking For: Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions Works independently; receives minimal guidance Acts as a resource for colleagues with less experience Represents the level at which career may stabilize for many years or even until retirement Contributes to process improvements Typically resolves problems...

Position: Physcial Design Engineer Job Description: Job Description What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor’s...

Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor's degree...

Position: Design Verification Engineer(eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect  Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience  Represents the...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...