3 senior electrical engineer jobs found

Position: Embedded Engineer (eInfochip Inc) Job Description: NOTE: This role will perform work covered by International Traffic in Arms Regulations. Viable candidates for this position must be eligible for an export license or be a U.S. Person (which includes but is not limited to U.S. citizens or nationals, lawful permanent residents, refugees, and asylees). What You'll Be Doing: Compliance Requirement: Must be ITAR Compliant (U.S. Person – Citizen/Green card) Hands-on experience with Qualcomm QCS platforms (QCS6490, QCS8550, QCS5430, QCS610, QCS8250 or similar) Strong Embedded Linux development experience Expertise in C/C++ programming Experience with board bring-up and hardware-software integration BSP, Linux Kernel, Device Tree, and Device Driver development Experience debugging bootloader, kernel, and platform bring-up issues Familiarity with ARM-based architectures What we are looking for: Experience interfacing peripherals such as UART, SPI, I2C,...

Position: Physcial Design Engineer Job Description: Job Description What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor’s...

Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor's degree...