3 senior field applications engineer jobs found

Basic Qualifications Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.   CLEARANCE REQUIREMENTS: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position General Dynamics Mission Systems has an immediate opening for an Advanced FPGA Engineer located in our Bloomington, MN location.   Duties and Tasks: Responsible for definition, design, verification and documentation for Advance FPGA (Field Programmable Gate...

Basic Qualifications Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience. Agile experience preferred.   CLEARANCE REQUIREMENTS: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Job Description:  General Dynamics Mission Systems has an opening for a Senior Advanced FPGA Engineer in Bloomington, MN.   Duties and Tasks: Responsible for definition, design, verification and documentation for FPGA...

Position: Senior Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Testbenches: Build scalable verification environments using UVM and SystemVerilog. Planning: Create detailed verification plans from architectural specifications. Execution: Write, run, and debug constrained-random tests and directed tests. Coverage: Define, measure, and close functional and code coverage metrics. Gate-Level: Run gate-level simulations to verify power-up and timing states. Automation: Develop scripts to automate regression runs and triage failures. What We Are Looking For: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Languages: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl). Methodology: Hands-on experience with UVM (Universal Verification Methodology) Tools: Experience with industry-standard simulators Cadence Xcelium preferred, but experience with Synopsys...