8 data engineer jobs found in San Jose, CA

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to...

Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT...

Basic Qualifications Bachelor's degree in Business, a technical field or equivalent experience plus a minimum of 5 years related experience is required. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Developing mission-critical systems that help keep people safe is what we do. At General Dynamics Mission Systems, you’ll be part of the team that helps heroes make a true impact. The work we do is important. The challenges we face are career-defining. The opportunity we can offer is one-of-a-kind. We apply advanced technologies such as Artificial Intelligence, Blockchain, AR/VR, Cloud Native and...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Position: Design Verification Engineer IV Job Description: Principal Accountabilities * Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development  * Develop complex self checking test benches with constraint random stimulus generation. * Architect SoC test FW and create test plan documentation to cover ASIC features. * Develop and debug SoC ASIC platform test FW and specific tests in C/C++. * Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification objective. * Develop/modify scripts to automate the verification process. * Develop verification environment including environment assumptions, assertions, and cover properties in context of the...

Position: Design Verification Engineer Job Description: Principal Accountabilities * Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect * Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience ● Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience ● Represents the level at which career may stabilize for many years or even until retirement ● Contributes to process improvements ● Typically resolves problems using existing solutions ● Provides informal...

Basic Qualifications Bachelor’s degree or equivalent is required plus a minimum of 8 years relevant experience; or Master's degree plus a minimum of 6 years relevant experience to meet managerial expectations. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is required at time of hire. The selected candidate must be able to obtain a Polygraph within a reasonable amount of time from date of hire.  Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position The responsibility is career-defining. So is the opportunity. At General Dynamics Mission Systems, we invent the technologies, products and services, that help our nation’s heroes keep our nation safe. The work is so advanced, our...

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote)  What will you do: Strong expertise on Arteris/ NOC Design Toolset  At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C based processor Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively What we are looking for: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. Experience in complete verification cycle which includes development of test plan,  BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great...