15 cloud engineer jobs found

Overview LMI is seeking a Senior Full Stack Software Engineer to support a Department of War mission partner on a digital modernization effort. This role sustains and modernizes government-owned business applications built on the Microsoft technology stack, keeping mission-critical .NET applications running reliably while helping re-engineer and migrate them into a secure AWS GovCloud environment. The engineer will work across the full stack, from SQL Server data layers to React front ends, within a DevSecOps pipeline. This is a largely remote position; however, candidates must reside in the vicinity of San Diego, CA to support periodic onsite collaboration.   This position requires an active Secret clearance .   LMI is a new breed of digital solutions provider dedicated to accelerating government impact with innovation and speed. Investing in technology and prototypes ahead of need, LMI brings commercial-grade platforms and mission-ready AI to...

Position: Embedded Firmware Engineer (eInfochips Inc) Job Description: NOTE: This role will perform work covered by International Traffic in Arms Regulations. Viable candidates for this position must be eligible for an export license or be a U.S. Person (which includes but is not limited to U.S. citizens or nationals, lawful permanent residents, refugees, and asylees). What You'll Be Doing: This is similar role is similar to embedded network engineer experienced  DO-178C  SOI-2 Dev Engineer to support certification of  Time-Sensitive Networking (TSN)  software for safety-critical avionics platforms. The engineer will participate in Software Development Reviews (SOI-2) by evaluating software requirements, architecture, detailed design, traceability, and compliance with DO-178C objectives. The role involves reviewing  TSN software components such as IEEE 802.1AS (gPTP), IEEE 802.1Qbv Time-Aware Shaper, IEEE 802.1Qav Credit-Based Shaper, IEEE 802.1CB FRER, ENETC...

Position: Design For Test Engineer III (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Description: Lockheed Martin Space will be hosting an invitation-only hiring event in very early September in Sunnyvale, CA. This requisition is to capture Level 2 through Level 3 Architecture & Algorithms / Agentic AI Machine Learning Engineer candidates to invite to the hiring event. We will be reviewing all Architecture & Algorithms / Agentic AI Machine Learning Engineer applicant resumes, contacting those that meet all of the Basic Qualifications and Desired Skills and may be a fit for one of our open roles, and interviewing candidates for the appropriate level opportunities. If invited to the event, you will be provided with the details regarding date, time, and location of the invitation-only hiring event. We will be interviewing candidates at Level 2 through Level 3 for roles at the Space AI Talent Center. Candidates will be joining a cross-functional team of experts in research, data science, software development, physics, and mathematics. As a key member of...

Position: Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development. Develop complex self checking test benches with constraint random stimulus generation. Architect SoC test FW and create test plan documentation to cover ASIC features. Develop and debug SoC ASIC platform test FW and specific tests in C/C++. Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents. Implement and maintain integrated end-to-end formal verification flow for the formal verification objective....

Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. What we are looking for: Bachelor's degree...

Position: Design Verification Engineer(eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect  Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics. Job Complexity ● Requires in-depth knowledge and experience Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience  Represents the...

Position: FPGA Engineer Engineer (eInfochips) Job Description: Job Description Location: San Jose CA and Austin TX (Day-1 Onsite) Experience: 9+ Years What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals....

Position: ASIC Design Engineer (eInfochips) Job Description: Role:   Asic Design Engineer Location: Mountain View CA (Remote) Note:   Seeking candidate with Fusion Compiler and Scripting experince. What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing...

Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern...

Basic Qualifications High School Diploma or equivalent is required plus a minimum of 3 years of relevant experience.   CLEARANCE REQUIREMENTS: : Department of Defense Secret security clearance is preferred, but must be obtainable within a reasonable amount of time after hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Responsibilities for this Position Imagine a world-class engineering environment. Now add a team of exceptional talent along with technologies that are so advanced they’re often classified. That’s what you’ll find at General Dynamics Mission Systems. Here you’ll lead amazing engineers as they invent the technologies, products and services that help our service members,...

Description: WHAT WE'RE DOING We deliver innovative, time-critical, SME-level technical expertise to the C4ISR family of fielded ground systems that support our customers in the field. Our Field Engineers provide technical support to operations forward environments and sustain and maintain the infrastructure and integration activities for our delivered C2 Ground Systems. THE WORK In this critical role, you will: • Provide SME level field systems administration expertise to the sustained operations and maintenance of the fielded ground systems. • Join the Fielded Systems Engineering-IT team as a Field Service Representative (FSR) responsible for the day to day maintenance, trouble shooting, fault isolation, and analysis of complex computer and communications equipment supplied to our customers. • Perform system administration functions on a variety of systems to include physical and virtual; troubleshoot and resolve interoperability issues; troubleshoot and resolve user...

Basic Qualifications Bachelor's degree in Business, a technical field or equivalent experience plus a minimum of 5 years related experience is required. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Developing mission-critical systems that help keep people safe is what we do. At General Dynamics Mission Systems, you’ll be part of the team that helps heroes make a true impact. The work we do is important. The challenges we face are career-defining. The opportunity we can offer is one-of-a-kind. We apply advanced technologies such as Artificial Intelligence, Blockchain, AR/VR, Cloud Native and...

Basic Qualifications Associate’s degree in related discipline or equivalent is required plus a minimum of 1 year of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Help make the technologies, products and services that make a difference. That’s the opportunity that’s waiting for you at General Dynamics Mission Systems. We help our nation’s heroes keep our nation safe by creating solutions so advanced, they redefine innovation for the world. It’s an amazing challenge. And it’s waiting for you now. We apply advanced technologies such as Artificial Intelligence, Blockchain,...

Basic Qualifications Associate’s degree in related discipline or equivalent is required plus a minimum of 3 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Developing mission-critical systems that help keep people safe is what we do. At General Dynamics Mission Systems, you’ll be part of the team that helps heroes make a true impact. The work we do is important. The challenges we face are career-defining. The opportunity we can offer is one-of-a-kind. We apply advanced technologies such as Artificial Intelligence, Blockchain, AR/VR, Cloud Native and Quantum Physics...